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| MOTOROLA Freescale Semiconductor, Inc. Semiconductor Technical Data Order Number: MC33888FB/D Rev. 1.6, 06/2001 Advance Information Quad High Side and Octal Low Side Switch for Automotive This QHSOLSS is a single packaged combination of four discrete high-side FETs and an integrated IC consisting of eight low-side drivers with appropriate control, protection, and diagnostic features. The high-side drivers are useful for both internal and external vehicle lighting applications as well as capable of driving inductive solenoid loads. The low-side drivers are capable of controlling low current on/off type inductive loads, such as relays and solenoids as well as LED indicators and small lamps. The device will be useful in body control, instrumentation, and other high power switching applications and systems. * Operating Voltage Range from 6V to 27V * Maximum Breakdown Voltage greater than 41V * Protected in case of loss of ground, loss of Vbat * Enhanced -16V Reverse Battery Protection (MOSFETs turned ON) * Surface Mount Power Package * Dual 10m High Side, Dual 40m High Side, Octal 500m Low Side * Configurable SPI and/Or Direct High Side Control * SPI Low Side Control with Single Configurable Direct Input * SPI or Direct Fed Watchdog * SPI Diagnostics * Individual Overtemperature Protection with Hysteresis * Configurable Open Load Detection in Off-State * Short-Circuit Protection to ground and to Vbat. * Configurable High Side Current Sense * Configurable High Side Current limitation * Under and Over Voltage Protection * Standby Current less than 80A at Vbat<14V and Tj<85C. MC33888FB SOLID STATE RELAY FOR AUTOMOTIVE APPLICATIONS SEMICONDUCTOR TECHNICAL DATA MO188 Jedec Package Freescale Semiconductor, Inc... PACKAGE MO188 64 pins 0.65 pitch Simplified Application Schematic Vbat Battery Vdd (5V) 10k FLTB IHS0, IHS1, 8x 0.5 IHS2, IHS3 ILS RSTB MC33888FB SPI 40m WDin CSNS2-3 CSNS0-1 FSI Rc2 Vdd 8xRelay or Led M C U 4 A/D A/D 40m 10m 10m 65W 65W 21W 5W 21W 5W Rc1 This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc., 2001. All rights reserved. For More Information On This Product, Go to: www.freescale.com TM MC33888FB Freescale Semiconductor, Inc. Figure 1. Internal Block Diagram VPW R VPW RT G ate C ontrol & Fau lt C SB SCLK SO SI VDD 40m 40m 10m H S3 H S2 H S1 SPI G ate C ontrol & Fau lt G ate C ontrol & Fau lt ILIM H S0 10m G ate Control Vpwr C urrent Sense C urrent Sense C SN S2-3 Freescale Semiconductor, Inc... IHS0 IHS1 IHS2 IHS3 ILS FLT B W DIN W AK E FSI O ver tem p Open Load (O FF state) C urrent Sense C urrent Sense C SN S0-1 LO G IC Gate C ontrol C lam p Over tem p RST B ILIM Internal Bias Supply W atchdog O pen Load x8 LS4 LS5 LS6 LS7 LS8 LS9 LS10 LS11 GND FIG URE 1: Q H SO LS S BLO C K DIAG R AM VPWRT CSNS0-1 IHS0 IHS1 WAKE RSTB 64 FSI WDIN FLTB VPWR LS4 GND LS5 LS6 GND LS7 LS8 GND LS9 LS10 GND LS11 VDD SO CSB SCLK 1 1 VPWRT HS2 NC NC NC 53 52 52 NC NC NC HS0 Pinout Description HS1 NC NC NC 20 20 21 32 33 33 VPWRT CSNS2-3 IHS2 IHS3 ILS SI NC NC NC For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive VPWRT HS3 2 MC33888FB Freescale Semiconductor, Inc. PINS FUNCTION DESCRIPTION Pin Number 6,9,12,15 4 43-49 36-42 pin name GND VPWR HS0 HS1 Description Ground. These pins serve as the ground for the source of the low-side output transistors as well as the logic portion of the device. Battery Voltage Each pin is the source of a 10m Ohm FET, high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS pins depending on the internal configuration. These outputs are current limited and thermally protected. During failsafe mode, output HS0 will be turned on until the device is reinitialized and then immediately followed by normal operation. Each pin is the source of a 40m Ohm FET, high-side driver which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS pins depending on the internal configuration. These outputs are current limited and thermally protected. During failsafe mode, output HS2 will be turned on until the device is reinitialized and then immediately followed by normal operation. Each High-Side Input pin is used to directly control only one designated HSO output. These inputs may or may not be activated depending upon the configured state of the internal logic. The Current Sense pins deliver a ratioed amount of the high-side output currents that can be used to generate signal ground referenced output voltages for use by the microcontroller. Each respective CSNS pin can be configured via SPI to deliver current from either of the two assigned outputs, or the currents could be the sum of the two. Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or HS3 are sensed via CSNS2-3. Each LS pin is one 0.6 Ohm low-side output FET drain which pulls current through the connected loads. Each of the outputs are actively clamped at 53V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 500mA. Each LS pin is one 0.6 Ohm low-side output FET drain which pulls current through the connected loads. Each of the outputs are actively clamped at 53V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 800mA The low-side input pin is used to directly control a number of the low-side devices as configured by SPI. This pin may or may not be activated depending upon the configured state of the internal logic. The Serial Clock Pin is connected to the SCLK pin of the master device which is a bit (shift) clock for the SPI port. It transitions 1 time per bit transferred at an operating frequency, fSPI and is idle between command transfers. It is 50% duty cycle, and has CMOS logic levels. This signal is used to shift data to and from the device.. The Serial Input is connected to the SPI Serial Data Output pin of the master device from which it receives output command data. This input has an internal active pulldown and requires CMOS logic levels. The serial data transmitted on this line is a 16 bit control command sent MSB first, which controls the twelve output channels. Bits D0-D3 control the high-side outputs HS0-HS3, respectively. Bits D4-D11 control the low-side outputs LS4-LS11, respectively. The master will ensure that data is available on the falling edge of SCLK. 56, 57 28, 29 HS2 HS3 Freescale Semiconductor, Inc... 61 62 24 23 60 25 IHS0 IHS1 IHS2 IHS3 CSNS0-1, CSNS2-3 5 8 11 14 7 10 13 16 22 LS4 LS6 LS8 LS10 LS5 LS7 LS9 LS11 ILS 20 SCLK 21 SI For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 3 MC33888FB Freescale Semiconductor, Inc. PINS FUNCTION DESCRIPTION 18 SO The Serial Output pin is connected to the SPI Serial Data Input pin of the master device or to the SI pin of the next device in a daisy chain. This output will remain tristated unless the device is selected by a low CSB pin. The output signal generated will have CMOS logic levels and the output data will transition on the rising edges of SCLK. The serial output data provides fault information for each output and is returned MSB first when the device is addressed. Fault bit assignments for return data are as follows: OD11 through OD0 are output fault bits for outputs 11 through 0, respectively. The Chip Select Bar pin is connected to a chip select output of an LSI IC. This IC controls which device is addressed by pulling the CSB pin of the desired device low, enabling the SPI communication with the device, while other devices on the serial link keep their serial outputs tri-stated. This input has an internal active pull-up and requires CMOS logic levels. The Reset pin is used to initialize the device configuration and fault registers, as well as place the device in a low current standby mode. This pin also starts the watchdog timeout when transitioned from logic L to logic H. This pin should not be allowed 19 CSB 64 RSTB Freescale Semiconductor, Inc... to be at logic H until the VCC is in regulation. This input has an internal passive pull-down. 63 WAKE This pin is a logic input that starts the device watchdog timeout when brought to a logic H. This pin will have an internal clamp which will protect the pin from high voltages when current is limited with an external resistor.This input has a passive internal pull-down. 2 WDIN The Watchdog Input pin is a CMOS logic level input that is used to monitor system operation. If the incoming watchdog signal does not transition within the normal watchdog timeout range, then the device will operate in the failsafe mode.This input has an active internal pull-down. 17 3 1 VDD FLTB FSI SPI logic power supply. The Fault output is an open drain indication that goes active low when a fault mode is detected by the device. Specific device fault indication is given via the SO pin. The FailSafe Input pin level determines the state of the outputs after a watchdog timeout occurs. This pin has an internal pull-up. If the FSI pin is left to float to a logic H, then HS0 and HS2 will turn on when in the failsafe state. If the FSI pin is tied to GND, then the watchdog circuit and failsafe operation will be disabled, thus allow- ing operation without a watchdog signal. 30,31,32 33,34,35 50,51,52 53,54,55 26, 27, 58, 59, TAB NC1 NC2 NC3 NC4 VPWRT These pins are not connected to the die. Although the NCx pins can be tied to any potential (or left to float), all pins sharing the same NCx designation must be tied to the same potential because they are internally connected together. These pins are tied to the backside TAB For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 4 Freescale MC33888FB Semiconductor, Inc. MAXIMUM RATINGS Parameter Power Supply Voltage Steady State Input Pin Voltage (Note 1) WAKE Input Pin Clamp Current LS 4,6,8,10 Continuous Per Output Current (Note 2) LS 5,7,9,11 Continuous Per Output Current (Note 2) HS0,1 Continuous Per Output Current HS2,3 Continuous Per Output Current (Note 3) HS0,1 Output Clamp Energy (Note 4) HS2,3 Output Clamp Energy (Note 5) LS Output Clamp Energy (Note 6) Storage Temperature Operating Junction Temperature Control Die Thermal Resistance (C/W) One LS on All LS on Power Die Thermal Resistance (C/W) One HS2,3 on All HSx on Ambient Thermal Resistance ESD Voltage Human Body Model (Note 7) Machine Model (Note 8) Module (Note 9) (Note 3) Symbol VPWR(sus) VIN WICI IOUTLS4,6,8,10 IOUTLS5,7,9,11 IOUTHS0,1 IOUTHS2,3 EHS0,1 EHS2,3 ELS Tstg Tjunc theta Cjc 12 5 theta Pjc 4 2 theta ja VESD1 VESD2 VESD3 2000 200 10000 C/W C/W C/W V V V C/W Value -16 to 41 -0.3 to 7.0 2.5 500 800 10 5 1.5 1.2 50 -55 to 150 -40 to 150 Unit V V mA mA mA A A J J mJ Deg C Deg C Freescale Semiconductor, Inc... NOTES: 1 Exceeding voltage limits on SCLK, SI, CSB, WDin, RSTB, IHS, FSI or ILS pins may cause permanent damage to the device. 2 Low-side output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125 Deg C ambient temperature will require maximum output current computation using package thermal resistances 3 High-side output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125 Deg C ambient temperature will require maximum output current computation using package thermal resistances 4 Active HS0,1 clamp energy using the following conditions: single pulse data pending 5 Active HS2,3 clamp energy using the following conditions: single pulse data pending 6 Active LS clamp energy using the following conditions: single non-repetitive pulse, 450mA, Tj=150C 7 ESD1 testing is performed in accordance with the Human Body Model (Czap = 100pF, Rzap = 1500Ohms ) 8 ESD2 testing is performed in accordance with the Machine Model (Czap = 100pF, Rzap = 0Ohm) 9 ESD3 testing is performed in accordance with the system module specification and will include at least 0.01uF of capacitance external to the device on each tested output (HS0-3, LS4-11, VPWR) For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 5 ELECTRICAL CHARACTERISTICS (VPWR from 6 to 27V, VDD from 4.5V to 5.5V and Tj from -40 to 150C, unless otherwise noted. Characteristic STATIC CHARACTERISTICS Supply Voltage Range Full Operational VPWR Supply Current VPWR Supply Current (all Outputs OFF, Open Load Detect Disabled, WAKE=H, RSTB=H) Sleep State Supply Current ( VPWR < 14V, RSTB <0.5V, WAKE<0.5V) Tj=85C Tj=25C Logic Supply Voltage Range Logic Supply Current Logic Supply Sleep State Current Sleep State LS Output Leakage Current (per LS Output, RSTB = L) Tj=85C Tj=25C Overvoltage Shutdown Overvoltage Shutdown Hysteresis Undervoltage Output Shutdown (Note 1) Undervoltage Power On Reset (Note 2) Undervoltage Shutdown Hysteresis Current Sense Ratio: CSNS0-1/HS0, (CSNS0-1/HS1) (VPWR=9V-16V, CNS <4.5V) Current Sense Ratio (CSR0-1) Accuracy HS0,1 Output Current: 1A 2A 5A 6.5A 10A Current Sense Ratio: CSNS2-3/HS2, (CSNS2-3/HS3) ( VPWR=9V-16, CNS <4.5V) Current Sense Ratio (CSR2-3) Accuracy HS2,3 Output Current: 0.5A 1A 3A 3.7A 5A Max Current Sense Voltage Clamp (ICNS=15mA) VPWR IPWR(on) IPWR(sby) 6.0 27.0 20 5 V mA mA Symbol Min Typ Max Unit Freescale MC33888FB Semiconductor, Inc. IPWR(ss) 80 25 VDD IDD(on) IDD(ss) LSLK(ss) 3 1 VPWROV VPWROV(hyst) VPWRUV UVPOR VPWRUV(hyst) CSR0-1 CSA0-1 % -35 -19 -14 -12 -9 CSR2-3 CSA2-3 % -30 -19 -13.5 -12 -9 SVmax 4.5 6 +30 +19 +13.5 +12 +9 7 V 1/880 +35 +19 +14 +12 +9 0.1 1/1400 28 0.2 5.0 32 0.8 5.5 36 1.5 6.0 5.0 0.5 uA uA V V V V V 4.5 5.0 5.5 5 5 uA uA V mA uA Freescale Semiconductor, Inc... For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 6 Freescale MC33888FB Semiconductor, Inc. HS0,1 POWER OUTPUT CHARACTERISTICS HS0,1 Drain-to-Source ON Resistance (IOUT=5.5A,TJ=25 Deg C) VPWR = 6.0V VPWR = 9.0V VPWR = 13V HS0,1 Drain-to-Source ON Resistance (Iout=5.5A, TJ=150 Deg C) VPWR=6.0V VPWR=9.0V VPWR=13V HS0,1 Reverse Battery Source-to-Drain ON Resistance (Iout=-5.5A, TJ=25 Deg C) VPWR=-12V Output Self Limiting Peak Current Outputs ON, Vout=0.3V Outputs ON, Vout=4.0V Output Self Limiting Sustain Current Outputs ON, Vout=0.3V Outputs ON, Vout=4.0V Open Load Detect Current (Note 3) Output Fault Detect Threshold Output Programmed OFF Output Negative Clamp Voltage 0.5A<=Iout<=2A, Output OFF Over-temperature Shutdown (Outputs OFF) (Note 6) Over-temperature Shutdown Hysteresis (Note 6) HS2,3 POWER OUTPUT CHARACTERISTICS HS2,3 Drain-to-Source ON Resistance (IOUT=4.5A,TJ=25 Deg C) VPWR = 6V VPWR = 9.0V VPWR = 13V HS2,3 Drain-to-Source ON Resistance (Iout=4.5A, TJ=150 Deg C) VPWR=6V VPWR=9.0V VPWR=13V HS2,3 Reverse Battery Source-to-Drain ON Resistance (Iout=-4.5A, TJ=25 Deg C) VPWR=-12V Output Self Limiting Peak Current Outputs ON, Vout=0.3V Outputs ON, Vout=4.0V Output Self Limiting Sustain Current Outputs ON, Vout=0.3V Outputs ON, Vout=4.0V Open Load Detect Current (Note 3) HS23RON25 0.08 0.04 0.04 HS23RON150 0.136 0.068 0.068 HS23RonRev Ohms Ohms Ohms Ohms Ohms Ohms HS01RON25 0.020 0.01 0.01 HS01RON150 0.034 0.017 0.017 HS01RONRev Ohms Ohms Ohms Ohms Ohms Ohms 0.020 HS01ilimpk 1 35 HS01ilimsus 1 15 HS01OLDC HS01OLDV HS01VCL HS01TLIM TLIM(hyst) 30 2 -20 160 10 170 20 190 30 3 24 30 30 100 4 10 40 60 60 Ohms A Freescale Semiconductor, Inc... A uA V V Deg C Deg C 0.08 HS23ilimpk 0.5 15 HS23ilimsus 0.5 6 HS23OLDC 30 11 15 15 100 6 20 35 35 Ohms A A uA For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 7 Freescale MC33888FB Semiconductor, Inc. Output Fault Detect Threshold (Note 4) Output Programmed OFF Output Negative Clamp Voltage 0.5A<=Iout<=2A, Outputs OFF Over-temperature Shutdown (Outputs OFF) (Note 6) Over-temperature Shutdown Hysteresis (Note 6) LOW-SIDE POWER OUTPUT CHARACTERISTICS Drain-to-Source ON Resistance (IOUT=0.3A,TJ=25 Deg C) VPWR = 6.0V VPWR = 9.0V VPWR = 13V Drain-to-Source ON Resistance (Iout=0.3A, TJ=150 Deg C) VPWR=6.0V VPWR=9.0V VPWR=13V LS4,6,8,10 Output Self Limiting Current Outputs Programmed ON, Vout=3.0V LS5,7,9,11 Output Self Limiting Current Outputs Programmed ON, Vout=3.0V Output OFF Open Load Detect Current (Note 3) Output Programmed OFF, Vout=3.0V Output Fault Detect Threshold (Note 5) Output Programmed OFF Output Clamp Voltage 2.0mA =< IOUT <= 200mA, Outputs OFF LS Body Diode Voltage (I=-300mA, Ta=150 C) Over-temperature Shutdown (Outputs OFF) (Note 6) Over-temperature Shutdown Hysteresis (Note 6) LSRon 1.0 0.7 0.6 LSRon 1.8 1.1 0.9 LS4,6,8,10 ILIM LS5,7,9,11 ILIM LSOLDC LSOLDV LSVCLMP LSBDV LSTLIM TLIM(hyst) 0.5 0.8 30 2.0 41 TBD 160 10 0.9 1.3 50 3.0 53 0.6 170 20 1.4 1.9 100 4.0 60 TBD 190 30 Ohms Ohms Ohms A A uA V V V Deg C Deg C Ohms Ohms Ohms HS23OLDV HS23VCL HS23TLIM TLIM(hyst) 2 -20 160 10 170 20 190 30 3 4 V V Deg C Deg C Freescale Semiconductor, Inc... NOTES: 1 SPI I/O and internal logic operational. Outputs will recover in instructed state when VPWR voltage level returns to normal as long as the level does not go below UVPOR. 2 VPWR Voltage levels less than UVPOR will result in a reinitialization of all internal logic when the level returns to normal levels. 3 Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 4 Output fault detect threshold with outputs programmed OFF. 5 Output fault detect threshold with outputs programmed OFF. For the LS Outputs, fault detect thresholds are the same for output open and battery shorts. 6 Guaranteed by Design; not production tested. DIGITAL INTERFACE TIMING Characteristic Input Logic High Voltage (Note 1) Input Logic Low Voltage (Note 1) Input Logic Voltage Hysteresis (SI, CSB, SCLK, IHS, ILS) (Note 2) Input Logic Pulldown Current (SI, SCLK, IHS, ILS, WDIN) Symbol VIH VIL Vin(hyst) Idwn Min 3.5 Typ Max Unit V 1.0 100 5 350 750 20 V mV uA For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 8 Freescale MC33888FB Semiconductor, Inc. Input Logic Pulldown Resistor (WAKE, RSTB) Input Logic Pullup Current (CSB, FSI, Vin=3.5V) (Note 5) Wake Input Clamp Voltage ( WICI < 2.5mA) (Note 4) Wake Input Forward Voltage (WICI = - 2.5mA) SO High State Output Voltage (IOH=1.0 mA) FLTB, SO Low State Output Voltage (IOL=-1.6mA) SO Tri-State Leakage Current (CSB 3.5V) Input Capacitance (Note 3) SO, FLTB Tri-State Capacitance (Note 2) NOTES: Rdwn Iup WICV WIFV VSOH VSOL SOLK Cin CSO 100 5 7 -2 0.8VDD 200 400 20 14 -0.3 kOhm uA V V V 0.2 -5 0 4 0.4 5 12 20 V uA pF pF Freescale Semiconductor, Inc... 1. Upper and lower logic threshold voltage range applies to SI, CSB, SCLK, RSTB, IHS0-3, ILS, WAKE and WDIN input signals.The WAKE, FSI, and RSTB signals are derived from an internal supply 2. Parameter is guaranteed by design but is not production tested. 3. Input capacitance of SI, CSB, SCLK, RSTB, IHS0-3, ILS, WAKE and WDIN. This parameter is guaranteed by process monitor but is not production tested. 4. The current must be limited by a series resistance when using voltages higher than the WICV. 5. The CSB is pulled up to VDD. POWER OUTPUT TIMING HS Output Rising Slew Rate (Note 1) HS Output Falling Slew Rate (Note 1) LS & HS Output Turn ON delay Time (Note 2) LS & HS Output Turn OFF delay Time (Note 3) Direct Input Switching Frequecy LS Output Fault Delay Timer (Note 4) Watchdog timeout (Note 5) LS Output Rise Time (Note 6) LS Output Fall Time (Note 6) Peak Current Limit Timer (Note 7) Notes SRr SRf Tdly(on) Tdly(off) PWMf Tdly(flt) wdto LSrt LSft Tpct 0.1 0.1 1.0 1.0 0.3 0.3 1 1 200 200 125 V/uS V/uS uS uS Hz uS mS uS uS mS 70 340 1 1 40 150 524 250 707 10 10 70 100 1. For HS Output Rise and Fall time respectively, measured across a 5 Ohm resistive load at 10% to 90% voltage points. These parameters are guaranteed by process monitor. 2. For LS Outputs, turn ON delay time measured from rising edge of CSB to 90% of output OFF Vout with RL=27 Ohm resistive load. For HS Outputs, turn ON delay time measured from rising edge of CSB to 90% of output OFF Vout with RL=5 Ohm resistive load. 3. For LS Output, turn OFF delay time measured from rising edge of CSB to 10% of output OFF Vout voltage with RL=27 Ohm resistive load. For HS Output, turn OFF delay time measured from rising edge of CSB to 10% of output OFF Vout voltage with RL=5 Ohm resistive load. 4. Propagation time of Short Fault Disable Report Delay measured from rising edge of CSB to Output disabled, LS=5.0V, and device configured for LS output over current latchoff using CLOCCR. 5. Wdto delay measured from the rising edge of WAKE or RSTB from the sleep state, to the HS0,1 turn-on with the outputs driven OFF and the FSI floating. The accuracy of wdto is maintained for all configured watchdog timeouts. 6. For LS Output Rise and Fall time respectively, measured across a 27 Ohm resistive load at 30% to 70% and 70% to 30% voltage points. 7. Tpct measured from the rising edge of CSB to 90% of HSxxilimpk when the peak current limit is enabled. For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 9 Freescale MC33888FB Semiconductor, Inc. SPI INTERFACE TIMING( TJ FROM -40 TO 150C, AND SYMMETRICAL 50% DUTY CYCLE SCLK CLOCK PERIOD OF 333 NS) Recommended Frequency of SPI Operation Required Low State Duration for RSTB (Note 1) Falling edge of CSB to Rising Edge of SCLK (Required Setup Time) (Note 2) Falling edge of SCLK to Rising Edge of CSB (Required Setup Time) (Note 2) SI to Falling Edge of SCLK (Required Setup Time) (Note 2) Falling Edge of SCLK to SI (Required Hold Time) (Note 2) SO Rise Time (CL=200pF) SO Fall Time (CL=200pF) SI, CSB, SCLK, Incoming Signal Rise Time (Note 3) SI, CSB, SCLK, Incoming Signal Fall Time (Note 3) Time from Falling Edge of CSB to SO Low Impedance (Note 4) Time from Rising Edge of CSB to SO High Impedance (Note 5) Time from Rising Edge of SCLK to SO Data Valid (Note 6) 0.2VDD<=SO>=0.8VDD, CL = 200 pF fSPI TwRSTB Tlead Tlag TSIsu TSI(hold) TrSO TfSO TrSI TfSI TSO(en) TSO(dis) Tvalid 50 50 50 25 25 25 25 65 65 3 167 167 167 83 83 50 50 50 50 145 145 105 MHz nS nS nS nS nS nS nS nS nS nS nS nS Freescale Semiconductor, Inc... Notes : 1. RSTB low duration measured with outputs enabled and going to OFF or disabled condition. 2. Maximum setup time required for the QHSOLSS is the minimum guaranteed time needed from the micro. 3. Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 4. Time required for output status data to be available for use at SO. 1 K Ohm pullup on CSB 5. Time required for output status data to be terminated at SO. 1 K Ohm pullup on CSB 6. Time required to obtain valid data out from SO following the rise of SCLK. For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 10 Freescale MC33888FB Semiconductor, Inc. SPI Interface and Protocol Description The SPI interface has full duplex, three wire synchronous data transfer and has four I/O lines associated with it: (SI, SO, SCLK, and CSB). The SI/SO pins of the QHSOLSS follow a first in / first out (D15 / D0) protocol with both input and output words transferring the most significant bit first. All inputs are compatible with 5.0 V CMOS logic levels. During SPI output control, a logic L in a message word will result in the designated output being turned off. Similarly, a logic H will turn on a corresponding output. All specific pin functions are specified as follows: SCLK - Clocks the internal shift registers of the QHSOLSS. The Serial Input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the SO Line Driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic low state whenever the Chip Select Bar (CSB) makes any transition. For this reason, it is recommended that the SCLK pin be kept in a logic L as long as the device is not accessed (CSB in logic H state). SCLK has an internal pull-down "Idwn" . When CSB is logic H, signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance). See the Data Transfer Timing diagram in Figure 2. SI - This pin is the input of Serial Instruction data. SI information is read in on the falling edge of SCLK. A sixteen bit stream of serial data is required on the SI pin, starting with D15, D14, etc, to D0. The twelve outputs of the QHSOLSS are configured and controlled using the 3 bit addressing scheme and the twelve assigned data bits designed into the QHSLOSS. SI has an internal pulldown "Idwn" . SO - The Serial Output data pin is a tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin is put into a logic L state. The SO data report the status of the outputs as well as provide the capability to reflect the state of the direct inputs. The SO pin changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. When an output is on or off and not faulted, the corresponding SO bit, OD0 - OD11, are a logic L. If the output is faulted, the corresponding SO state is a logic H. SO OD12-OD14 reflect the state of six various inputs (three at a time) depending upon the reported state of the previously written watchdog bit OD15. CSB - The Chip Select (Bar) pin enables communication with the Master device. When this pin is in a logic L state, the QHSOLSS is capable of transferring information to and receiving information from the Master. The QHSOLSS latches in data from the input shift registers to the addressed registers on the rising edge of CSB. The QHSOLSS transfers status information from the power outputs to the shift registers on the falling edge of CSB. The output driver on the SO pin is enabled when CSB is logic L. CSB is only transitioned from a logic H state to a logic L state when SCLK is a logic L. CSB has an internal pullup "Iup" . The QHSOLSS is capable of interfacing directly with a microcontroller, via the 16 bit SPI protocol described and specified below Figure 2. Data Transfer Timing . CSB Freescale Semiconductor, Inc... SCLK SI D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D 12 D 13 D14 D15 SO OD0 OD1 OD2 OD3 OD4 OD5 OD6 OD7 OD8 OD9 O D10 O D11 O D 12 OD13 OD14 O D15 NO TES: 1. 2. 3. R S T B is in a lo g ic H s ta te d u rin g th e a b o v e o p e ra tio n . D O , D 1 , D 2 , ... , a n d D 1 5 re la te to th e m o s t re c e n t o rd e r e d e n try o f p ro g ra m d a ta in to th e Q H S L O S S O D 0 , O D 1 , O D 2 , ..., a n d O D 1 5 re la te to th e firs t 1 6 b its o f o rd e re d fa u lt a n d s ta tu s d a ta o u t o f th e Q H S L O S S F IG U R E 2 a . S IN G L E 1 6 b it W O R D S P I C O M M U N IC A T IO N CSB SCLK SI D0 D1 D2 D13 D14 D 15 D0* D1* D2* D13* D 14* D 15* SO D0* D1* D2* D 13* D14* D15* OD0 OD2 OD3 OD13 OD14 O D15 NO TES: 1. 2. 3. 4. R S T B is in a lo g ic H s t a t e d u r in g t h e a b o v e o p e r a t io n . D O , D 1 , D 2 , . . . , a n d D 1 5 r e la t e t o t h e m o s t r e c e n t o r d e r e d e n t r y o f p r o g r a m d a t a in t o t h e Q H S L O S S D 0 * , D 1 * , D 2 * , . .. , a n d D 1 5 * r e la t e t o t h e f ir s t 1 6 b it s o f o r d e r e d e n t r y d a t a in t o t h e Q H S L O S S O D 0 , O D 1 , O D 2 , . . ., a n d O D 1 5 r e la t e t o t h e f ir s t 1 6 b its o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e Q H S L O S S FIGUREFi DATA TRANSFER TIMING 2. F IG U R E 2 b . M U L T IP L E 1 6 b it W O R D S P I C O M M U N IC A T IO N For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 11 Freescale MC33888FB Semiconductor, Inc. SPI Interface and Protocol Description SI COMMUNICATION SPI communication will be accomplished via 16bit messages. A message is transmitted by the master starting with the MSB D15 and ending with the LSB D0. Each incoming command message on the SI pin can be interpreted using the following bit assignment: the first twelve LSBs, D0-11, control each of the twelve outputs, the next three bits, D12-D14, determine the command mode, and the MSB, D15, is the watchdog bit (see TABLE 1). Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16bits. If an attempt is made to latch in a message that is not 16bits, then it is ignored. The QHSOLSS has 6 registers which are used to configure the device and control the state of the four high-side and eight lowside outputs. The registers are addressed via D12-D14 of the incoming SPI word (see TABLE 1). Table 1 * SI MESSAGE BIT ASSIGNMENT BIT SIG MSB SI MESSAGE BIT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 MESSAGE BIT DESCRIPTION Watchdog in: toggled to satisfy watchdog requirements Register Address Bit: Register Address Bit Register Address Bit Used to Configure Low-Side Output LS11 Used to Configure Low-Side Output LS10 Used to Configure Low-Side Output LS9 Used to Configure Low-Side Output LS8 Used to Configure Low-Side Output LS7 Used to Configure Low-Side Output LS6 Used to Configure Low-Side Output LS5 (Watchdog timeout MSB during WDCSCR configuration) Used to Configure Low-Side Output LS4 (Watchdog timeout LSB during WDCSCR configuration) Used to Configure High-Side Output HS3 Used to Configure High-Side Output HS2 Used to Configure High-Side Output HS1 Used to Configure High-Side Output HS0 Freescale Semiconductor, Inc... The eight possible addresses (D12,D13,D14) and a description of their impact on the device operation is as follows (see TABLE 2): - Address LLL (SPI Output Control Register (SOCR)) - This register allows the master to control the outputs via the SPI. Incoming message bits D0-3 reflect the desired states of the high-side outputs HS0-HS3. Message bits D4-D11 reflect the desired state of the low-side outputs LS4-LS11 respectively. - Address LLH (Direct Input Control Register (DICR)) -This register is used by the master to enable direct input control of the outputs. For the outputs, a logic L on bits D0-D11 will enable the corresponding output for direct control. A logic H on a D0-D11 bit will disable the output from direct control. - Address LHL (Logic Function Control Register (LFCR)) - This register is used by the master to configure the relationship between the SOCR bits D0 - D11 and the Direct Inputs IHSx and ILS. While addressing this register (if the Direct Inputs were enabled for direct control with the DICR), a logic H on any or all of the D0-D3 bits will result in a Boolean AND of the For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 12 Freescale MC33888FB Semiconductor, Inc. SPI Interface and Protocol Description IHSx pin(s) with its (their) corresponding D0-D3 message bit(s) when addressing the SOCR. A logic H on any or all of the D4-D11 bits will result in a Boolean AND of the ILS and the corresponding D4-D11 message bits when addressing the SOCR. Similarly, a logic L on the D0-D3 pins will result in a Boolean OR of the IHSx pin(s) to their corresponding message bits when addressing the SOCR, and the ILS will be Boolean ORed with message bits D4 - D11 when addressing the SOCR (if ILS enabled). - Address LHH (Watchdog and Current Sense Configuration Register (WDCSCR)) - This register is used by the master to configure the Watchdog Timeout and the CSNS01 and CSNS23 pins. The Watchdog timeout is configured using bits D4 and D5. The state of D4 and D5 determine the divided value of the wdto. For example, if D4 and D5 are logic LL, respectively, then the wdto will be in the default state as specified in Table 10. A D4D5 of HL will result in a watchdog timeout of wdto / 2. Similarly, a D4D5 of LH results in a watchdog timeout of wdto / 4, and a D4D5 of HH results in a watchdog timeout of wdto / 8. Note that when D4D5 bits are programmed for the desired watchdog timeout period, the WDSPI bit should be toggled as well to insure that the new timeout period is programmed at the beginning of a new count sequence. CSNS01 is the current sense output for the HS0 and HS1 outputs. Similarly, the CSNS23 pin is the current sense output for the HS2 and HS3 outputs respectively. In this mode, a logic H on any or all of the message bits that control the HS outputs will result in the sensed current from the corresponding output to be directed out of the appropriate CSNS output. For example, if D0 and D1 are both logic H, then the sensed current from HS0 and HS1 will be summed into the CSNS01. If D2 is logic H and D3 is logic L, then only the sensed current from HS2 will be directed out of CSNS23. - Address HLL (Open Load Configuration Register (OLCR)) - This register allows the master to configure each of the outputs for Open Load Fault detection. While in this mode, a logic H on any of the D0-D3 message bits will disable the corresponding outputs' circuitry that allows the device to detect open load faults while the output is off. For the Low side drivers, a logic H on any of the D4-D11 bits will enable the open load detection circuitry. This feature allows the master to minimize load current in some applications, and may be useful to diagnose output shorts to battery (for HS). - Address HLH (Current Limit Over Current Configuration Register (CLOCCR)) - This register allows the master to individually override the peak current limit levels for each of the High Side outputs. A logic H on any or all of the D0-D3 bit(s) results in the corresponding HSx to current limit at the sustain current limit level. This register also allows the master to enable or disable the over current shutdown of the Low Side outputs. A logic H on any or all ot the D4-D11 message bit(s) will result in the corresponding LSxx to latch off if the current exceeds ILIM after a timeout of tdly(flt). - Address HHL - Not presently used - Address HHH - This register is reserved for test and is not accessible via SPI during normal operation. Table 2 * ADDRESS AND CONFIGURATION BIT MAP HIGH-SIDE D0 HS 0 PW B0 A/ OB 0 CS 0 OLB 0 ILIM 0 Freescale Semiconductor, Inc... LOW-SIDE D3 HS 3 PW B3 A/ OB 3 CS 3 OLB 3 ILIM 3 ADDRESS D9 LS 9 PW B9 A/ OB 9 NA OL 9 OC 9 D10 LS 10 PW B10 A/ OB1 0 NA OL 10 OC 10 D11 LS 11 PW B11 A/ OB1 1 NA OL 11 OC 11 D 12 L L L D 13 L L H D 14 L H L WD D 15 X X X REG NAME D1 HS 1 PW B1 A/ OB 1 CS 1 OLB 1 ILIM 1 D2 HS 2 PW B2 A/ OB 2 CS 2 OLB 2 ILIM 2 D4 LS 4 PW B4 A/ OB4 WD L OL 4 OC 4 - D5 LS 5 PW B5 A/ OB 5 WD H OL 5 OC 5 - D6 LS 6 PW B6 A/ OB 6 NA OL 6 OC 6 - D7 LS 7 PW B7 A/ OB 7 NA OL 7 OC 7 - D8 LS 8 PW B8 A/ OB8 NA OL 8 OC 8 - SOCR DICR LFCR L H H H H H L L H H H L H L H X X X X X WDCSCR OLCR CLOCCR NOT USED TEST OT - WD ILIM PK ILIM For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 13 Freescale MC33888FB Semiconductor, Inc. SPI Interface and Protocol Description X : don't care NA Not Applicable SO Communication (see TABLE 3) When the CSB pin is pulled low, the output status register for each output is loaded into the output register and the fault data is clocked out MSB (OD15) first, as the new message data is clocked into the SI pin. OD15 reflects the state of the watchdog bit (D15) that was addressed during the prior SOCR communication. If the OD15 is logic L, then the following three MSBs (OD14, OD13, OD12) will reflect the logic states of the IHS0, IHS1 and FSI pins respectively. If the OD15 bit is logic H, then the following three bits will reflect the logic states of the IHS2, IHS3 and WAKE pins respectively. The next twelve bits clocked out of SO following a low transition of the CSB pin will reflect the state of each output, with a logic H in any of the bits indicating that the respective output experienced a fault condition prior to the CSB transition. Any bits clocked out of the SO pin after the first sixteen will be representative of the initial message bits that were clocked into the SI pin since the CSB pin first transitioned to a logic L; this feature is useful for daisy chaining devices as well as message verification. Following a CSB transition L to H, the device determines if the message was of a valid length (a valid message length is one that is a multiple of 16 bits) and if so, latches the data into the appropriate registers. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. Freescale Semiconductor, Inc... Table 3 * SO OUTPUT BIT ASSIGNMENT BIT SIG MSB SO MESSAGE BIT OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 LSB OD0 MESSAGE DISCRIPTION Reflects the state of the Watchdog bit from the previously clocked in message. If OD15 is logic L, then this bit will reflect the state of the direct input IHS0. If OD15 is logic H, then this bit will reflect the state of IHS2. If OD15 is logic L, then this bit will reflect the state of the direct input IHS1. If OD15 is logic H, then this bit will reflect the state of IHS3. If OD15 is logic L, then this bit will reflect the state of the input FSI. If OD15 is logic H, then this bit will reflect the state of the input WAKE. Reports the absence or presence of a fault on LS11 Reports the absence or presence of a fault on LS10 Reports the absence or presence of a fault on LS9 Reports the absence or presence of a fault on LS8 Reports the absence or presence of a fault on LS7 Reports the absence or presence of a fault on LS6 Reports the absence or presence of a fault on LS5 Reports the absence or presence of a fault on LS4 Reports the absence or presence of a fault on HS3 Reports the absence or presence of a fault on HS2 Reports the absence or presence of a fault on HS1 Reports the absence or presence of a fault on HS0 For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 14 MC33888FB Freescale Semiconductor, Inc. DEVICE DESCRIPTION WATCHDOG AND FAILSAFE OPERATION The watchdog is enabled and a timeout is started when the WAKE or RSTB transition from logic L to logic H. The WAKE input is capable of being pulled up to VPWR with a series limiting resistance that limits the internal clamp current. The timeout is a multiple of an internal oscillator . As long as the WDIN pin, or D15 of an incoming SPI message, is toggled within the minimum watchdog timeout, wdto (or a divided value configured during a WDCSCR message), then the device will operate normally. If the watchdog timeout occurs before the WD bit or WDIN pin is toggled, then the device will revert to a failsafe mode until the device is reinitialized (if the FSI pin is left disconnected). During failsafe mode, all outputs will be off except for HS0 and HS2, which will be driven on regardless of the state of the various direct inputs and modes. The device can be brought out of failsafe mode by transitioning the WAKE and RSTB pins from logic H to logic L. In the event that the WAKE pin was not transitioned to a logic H during normal operation and the watchdog times out, then the device can be brought out of failsafe by bringing the RSTB to a logic L. If the FSI pin is tied to GND, then the watchdog, and therefore failsafe operation, will be disabled (see TABLE 4). Table 4 * FAILSAFE OPERATION WAK E L H RSTB WDTO HS0 HS2 OTHER LSx, HSx OFF OFF COMMENTS Freescale Semiconductor, Inc... L L X NO OFF OFF OFF OFF Device is in Sleep Mode All outputs are OFF, when RSTB transitions to logic H, device is in Default Failsafe. Device reset into Default mode by transitioning WAKE to logic L Device in Normal Operating mode Failsafe. Device reset into Default mode by transitioning RSTB to logic L Device in Normal Operating Mode Failsafe. Device reset into Default mode by transitioning RSTB & WAKE to logic L H L L H H L H H H H YES NO YES NO YES ON S ON S ON ON S ON S ON OFF S OFF S OFF X: don't care S: state determined by SPI and/or Direct Input configurations. Assumptions: Normal operating Voltage and Junction Temperatures, FSI pin floating. DEFAULT MODE The default mode describes the state of the device after first applying battery or a reset transition from logic L to H prior to SPI communication. In the default mode, all of the outputs will be off (assuming that the direct inputs ILS and IHSx, and the WAKE pins are at logic L). All of the specific pin functions will operate as though all of the addressable configuration register bits were set to logic L. This means, for example, that all of the LS outputs will be controllable by the ILS pin, and that all HS outputs will be controllable via their respective IHS pins. During the Default Mode, all of the HS drivers will default with the open load detection enabled. All of the low side drivers will default with the open load detection disabled. This mode allows limited control of the QHSOLSS with the direct inputs in the absence of a SPI. FAULT LOGIC REQUIREMENTS The QHSOLSS indicates all of the following faults as they occur: over-temperature fault, open-load fault, over-current fault and an over-voltage fault. All of these faults, with the exception of the over-voltage, are output specific. The over-voltage fault is a global fault. The over-current fault is only reported for the low side outputs. The QHSOLSS low-side outputs incorporate an internal fault filter "Tdly(flt)".The fault timer filters noise and switching transients for over-current faults (when the output is on) and open load faults (when the output is off). All faults are latched and indicated For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 15 MC33888FB Freescale Semiconductor, Inc. DEVICE DESCRIPTION by a logic H for each output in the QHSOLSS status word (TABLE 3). ). If the fault is removed, the status bit for the faulted output will be cleared by a rising edge on CSB. The FLTB pin is driven to a logic L when a fault exists on any of the outputs. FLTB provided real time monitoring of the overvoltage fault. For the high side outputs, FLTB provides real time monitoring of the open-load and over-temp. For the low side outputs, the FLTB is latched to a logic L for open-load, over-temp, and over-current faults. The latch is cleared by toggling the state of the faulted output or by brinding RSTB low. OVER-TEMPERATURE FAULT REQUIREMENTS The QHSOLSS incorporates over-temperature detection and shutdown circuitry into each individual output structure. Overtemperature detection occurs when an output is in the on state. When an output is shutdown, due to an over-temperature condition, no other outputs is affected. The output experiencing the fault, is shutdown to protect itself from damage. A fault bit is loaded into the status register if the over-temp condition is removed, the fault bit is cleared upon the rising edge of CSB. For the LS outputs, the faulted output is latched OFF during an over-temp condition. If the temperature falls below the recovery level, "TLIM(hyst)", then the output can be turned back ON only after the output has first been commanded OFF either through the SPI or the ILS, depending on the logic configuration. For the HS output(s), an over-temperature condition will result in the output(s) turning OFF until the temperature falls below the TLIM(hyst). This cycle will continue indefinitely until action is taken by the master to shut the output(s) OFF. OVER-VOLTAGE FAULT REQUIREMENTS The QHSOLSS do shutdown all outputs during an over-voltage condition on the VPWR pin. The outputs remain in the off state, until the over-voltage condition is removed. Fault status for all outputs is latched into the status register. Following an overvoltage condition, the next write cycle sent by the SO pin of the QHSOLSS is logic H on OD0-OD11, indicating all outputs have shutdown. If the over-voltage condition is removed, the status register can be cleared by a rising edge on CSB. OPEN LOAD FAULT The QHSOLSS incorporates open-load detection circuitry on every output. A HS or LS Output Open Load Fault is detected and reported as a fault condition when the corresponding output is disabled (OFF) if it was configured for open load detection by setting the appropriate bit to logic L (HS0-HS3), or logic H (LS4-LS11) in the OLFCR register. The HS open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn off the output. If the open load fault is removed or if the faulted output is commanded ON, the status register can be cleared by a rising edge on CSB. Note that the device default state will enable the HS open load detection and disable the LS open load detection circuits, respectively. Figure 3. LS Output OFF Open Load Detect Q H SO LSS D E VIC E L OW = M osfet O 50 V PW Freescale Semiconductor, Inc... RL O U T PU V threshol 2.5V - OVER-CURRENT FAULT REQUIREMENTS: LS OUTPUT An over-current condition is defined as any current value greater than ILIM (500mA min value)for LS5, 7, 9, 11 and 800mA min value for LS4, 6, 8, 10). The status of the corresponding bit in the CLOCCR register determines whether a specific output will shutdown, or will continue to operate in an analog current limited mode, until either the over-current condition is removed or the thermal shutdown limit is reached (see Figure3). If the over-current shutdown mode is disabled, the fault reporting is disabled as well. For the LS output of interest, if a D4-D11 bit was set to a logic H in the OLCR register, the over-current protection shutdown circuitry will be enabled for that output. When a low side output is commanded ON either from the SPI or the ILS pin, the drain of the low side driver will be monitored for a voltage greater than the Fault Detect Threshold (3V typ). If the drain voltage exceeds this threshold, a timer will start and the output will be turned off and a fault latched in the status register after the timeout expires. The faulted output can be retried only by commanding the output OFF and back ON either through the SPI or the ILS pin, depending on the logic configuration. If the fault is gone, the retried output will return to normal operation and the status register For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 16 can be cleared on a rising edge of CSB. If the fault remains, the retried output will latch off after the fault timer expires and the fault bit will remain set in the status register. For the LS output of interest, if a D4-D11 bit was set to a logic L in the OLCR register, the output experiencing an over-current condition is not disabled until an over-temperature fault threshold has been reached. The specific output goes into an analog current limit mode of operation ILIM . The QHSOLSS uses over-temperature shutdown to protect all outputs in this mode of operation. If the over-current condition is removed before the output has reached its over-temperature limit, the output will function as if no fault has occurred. Note that each pair of Low Side Drivers, LS4-5, LS6-7, LS8-9, and LS10 -11 consist of a 500mA and 800mA output. As shown in the device pinout, each of these pairs of outputs share ground bondwires. The bondwires are not rated to handle both outputs in current limit mode simultaneously. OVER-CURRENT FAULT REQUIREMENTS: HS OUTPUT For the HS output of interest, the output current is limited to one of four levels depending upon : the type of HS output, the amount of time that has elapsed since the output was switched on, and the state of the CLOCCR register. Assuming that bits D0-D3 of the CLOCCR register are at logic L, the current limit levels of the outputs will be initially at their peak levels as specified by the HSxxilimpk. After the HS output is switched on, the peak current timer will start. After a period of time Tpct, the current limit level will change to the sustain levels HSxxilimsus. For the HS output of interest, if a D0-D3 bit of the CLOCCR is at logic H, then the assigned output will only current limit at the sustain level specified by HSxxilimsus. Current is limited until the over temperature circuitry shuts OFF the device. The device will turn ON automatically when the temperature fails below the TLIM(hyst). This cycle continues indefinitely until action is taken by the master to shut the output(s) OFF. REVERSE BATTERY REQUIREMENTS The LS and HS outputs survive the application of reverse battery as low as -16V. GROUND DISCONNECT PROTECTION In the event that the QHSOLSS ground is disconnected from load ground, the device protects itself and safely turns off the outputs, regardless of the state of the output at the time of disconnection. BATTERY DISCONNECT PROTECTION In the event that the QHSOLSS is disconnected from Vpwr, the device protects itself and safely turn off the outputs, regardless of the state of the output at the time of disconnection. UNDER-VOLTAGE SHUTDOWN REQUIREMENTS All outputs turn off at some battery voltage below 6.0V, however, as long as the level stays above 5.0V, the internal logic states within the device are designed to be sustained. This ensures that when the battery level then rises above 6.0V, the device will return to the state that it was in prior to the excursion between 5.0V and 6.0V (assuming that there was no SPI communication or direct input changes during the event). If the battery voltage falls to a level below 5.0V, then the internal logic is reinitialized and the device is then in the Default state upon the return of levels in excess of 6.0V. OUTPUT VOLTAGE CLAMPING Each output has an internal clamp to provide protection and dissipate the energy stored in inductive loads. Each clamp independently limits the drain to source voltage to the range specified in the table "Power output characteristics". MC33888FB Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go Octal Low Side Switch for Quad High Side and to: www.freescale.comAutomotive 17 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 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Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or un authorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the parts. Motorola and an Equal Employment Opportunity/Affirmative Action Employer. are registered trademarks of Motorola, Inc. Motorola, Inc. is How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Technical Information Center: 1-800-521-6274 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-344-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 HOME PAGE: http://www.motorola.com/semiconductors MC33888FB/D For More Information On This Product, Go to: www.freescale.com |
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